1. Field of the Invention
The present invention relates to a clock transferring apparatus for synchronizing a pattern signal with a variable clock that is oscillated based on an oscillation source different from that of the pattern signal and to a test apparatus having such clock transferring apparatus.
2. Related Art
As a test apparatus for testing a device-under-test such as a semiconductor circuit, there has been known a test apparatus that injects jitter to a test signal that is to be supplied to the device-under-test and measures a value of jitter that disables the device-under-test to normally operate. While the test apparatus generates the test signal based on a reference clock, there have been known a method of injecting jitter to the reference clock and a method of injecting jitter to the generated test signal in injecting jitter to the test signal.
FIG. 1 is a diagram for explaining a conventional test apparatus 200, wherein FIG. 1A shows a configuration of the test apparatus 200 that injects jitter to the reference clock and FIG. 1B shows a configuration of the test apparatus 200 that injects jitter to the test signal. The test apparatus 200 shown in FIG. 1A has a reference clock generating section 202, a pattern generating section 204 and a variable delay circuit 206. The reference clock generating section 202 generates the reference clock having an almost same period with that of the test signal that is to be applied to the device-under-test DUT and supplies it to each component of the test apparatus 200.
The pattern generating section 204 generates the test signal to be applied to the device-under-test DUT corresponding to the given reference clock. That is, it generates pulses of the test signal corresponding to pulses of the given reference clock. Therefore, it is possible to generate the test signal having a desirable period by controlling the period of the reference clock. The test apparatus 200 injects jitter to the test signal by generating the reference clock to which the jitter has been injected in the reference clock generating section 202. The variable delay circuit 206 controls the test signal so as to have a desirable phase and applies it to the device-under-test DUT.
The test apparatus 200 shown in FIG. 1 B has a reference clock generating section 208, a pattern generating section 204, a coarse delay section 210, a variable delay circuit 206 and an adding section 212. The reference clock generating section 208 generates a reference clock having a preset period and the pattern generating section 204 generates the test signal corresponding to the given reference clock. The coarse delay section 210 and the variable delay circuit 206 delay respective pulses of the test signal to control the period and phase of the test signal. The coarse delay section 210 delays integer times of the period of the reference clock among values of delay of the respective pulses of the test signal to be delayed and the variable delay circuit 206 delays by a value smaller than period of the reference clock among the values of delay. The adding section 212 accumulatively adds differences of the period of the test signal and the period of the reference clock to control the value of delay of the variable delay circuit 206. The test apparatus 200 injects jitter to the test signal by providing a voltage fluctuating circuit at an output end or by controlling the value of delay of the variable delay circuit 206. The applicant is presently unaware of related patent documents, so that their description will be omitted here.
However, it is difficult to design timing of the test apparatus 200 shown in FIG. 1A because the period of the reference clock supplied to each component is variable. That is, because the period of the reference clock given as an operating clock fluctuates, it is necessary to design the timing of each component so that they can operate at each period of the reference clock. Still more, it becomes more difficult to design the timing because the reference clock to which the jitter has been injected is supplied to each component.
Still more, while the test apparatus 200 shown in FIG. 1B injects jitter to the test signal by the voltage fluctuating circuit or the like, it is difficult to inject accurate jitter as compared to the case of injecting jitter in the reference clock generating section 208.